Nitride read only memory (NROM) arrays are known in the art, and are described in many patents. U.S. patent application Ser. No. 11/247,733 for example, assigned to the common assignee of the present invention, and whose disclosure is incorporated herein by reference, describes a dense planar virtual ground (VG) NROM array, composed of double polysilicon planar NROM cells. FIG. 1, reference to which is now made, shows a schematic top view of an exemplary dense planar VG array 10.
The virtual ground array architecture, as shown in FIG. 1, consists of a dense crisscrossing of word lines 19 and bit lines 22. Due to the high resistance of bit lines 22, contacts 26, which are connected to highly conductive metal lines, are employed to convey charge along bit lines when the distance the charge must travel is long. In a planar VG NROM array such as array 10, contacts 26 are typically located every 16 to 32 word lines.
Sufficient horizontal margins Mh and vertical margins Mv must be maintained between each contact 26 and the bit lines and word lines adjacent to it in order to ensure reliable operation of array 10. As further shown in FIG. 1, both margins Mh and Mv are affected when a contact, such as exemplary contact 26j, does not land squarely on its intended bit line location Lj during manufacture.
In the example shown in FIG. 1, where exemplary contact 26j lands below and to the right of location Lj, instead of directly on location Lj, margin Mvt, between the top edge of contact 26j and adjacent word line 19t increases to a length of Mvtj. Margin Mvb, between the bottom edge of contact 26j and adjacent word line 19b decreases to a length of Mvbj. Laterally, margin Mh, between the rightmost edge of contact 26j and adjacent bit line 22r decreases to a length of Mhj.
Misalignments between a contact 26 and a bit line 22 such as that exemplified by contact 26j in FIG. 1, result in a reduction of the distance between bit lines, due to doping of the substrate at the contact landing point. Thus leakage between bit lines becomes a serious problem.
Implementation of shallow trenchline isolation (STI) which is known in the art, between bit lines at the contact region, is a straightforward solution which can address the leakage between bit lines. However, the drawbacks of this solution include the complication of the manufacturing process and the possible requirement of additional horizontal and vertical margins, which carries a substantial die size penalty.